The term “transmitter” is used herein in a broad sense to denote any device capable of transmitting data over a serial link, and optionally also capable of performing additional functions which can include encoding and/or encrypting the data to be transmitted. The term “receiver” is used herein in a broad sense to denote any device capable of receiving data that has been transmitted over a serial link, and optionally also capable of performing additional functions, which can include decoding and/or decryption of the received data, and other operations related to decoding, reception, or decryption of the received data. For example, the term receiver can denote a transceiver that performs the functions of a transmitter as well as the functions of a receiver.
The expression “serial link” is used herein to denote a serial link (having any number of channels) or a channel of a serial link, where the term “channel” of a serial link denotes a portion of the link that is employed to transmit data in serial fashion (e.g., a conductor or conductor pair between a transmitter and receiver over which data are transmitted serially, either differentially or in single-ended fashion).
The term “stream” of data, as used herein, denotes that all the data are of the same type and is transmitted with the same clock frequency. In some cases, a channel of a serial link is employed to transmit one stream of data. In other cases, a channel of a serial link is employed to transmit more than one stream of data.
There are various, well-known serial links for transmitting video data and other data. One conventional serial link is known as a transition minimized differential signaling interface (“TMDS” link). This link is used primarily for high-speed transmission of video data from a set-top box to a television, and also for high-speed transmission of video data from a host processor (e.g., a personal computer) to a monitor. Among the characteristics of a TMDS link are the following:
1. video data are encoded and then transmitted as encoded words (each 8-bit word of digital video data is converted to an encoded 10-bit word before transmission);
2. the encoded video data and a video clock signal are transmitted as differential signals (the video clock and encoded video data are transmitted as differential signals over conductor pairs without the presence of a ground line); and
3. three conductor pairs are employed to transmit the encoded video, and a fourth conductor pair is employed to transmit the video clock signal.
Another serial link is the “High Definition Multimedia Interface” interface (“HDMI” link) developed Silicon Image, Inc., Matsushita Electric, Royal Philips Electronics, Sony Corporation, Thomson Multimedia, Toshiba Corporation, and Hitachi.
Another serial link is the “Digital Video Interface” (“DVI” link) adopted by the Digital Display Working Group. It has been proposed to use the cryptographic protocol known as the “High-bandwidth Digital Content Protection” (“HDCP”) protocol to encrypt digital video data to be transmitted over a DVI link, and to decrypt the encrypted video data at the DVI receiver. A DVI link can be implemented to include two TMDS links (which share a common conductor pair for transmitting a video clock signal) or one TMDS link, as well as additional control lines between the transmitter and receiver. We shall describe a DVI link (that includes one TMDS link) with reference to FIG. 1. The DVI link of FIG. 1 includes transmitter 1, receiver 3, and the following conductors between the transmitter and receiver: four conductor pairs (Channel 0, Channel 1, and Channel 2 for video data, and Channel C for a video clock signal), Display Data Channel (“DDC”) lines for bidirectional communication between the transmitter and a monitor associated with the receiver in accordance with the conventional Display Data Channel standard (the Video Electronics Standard Association's “Display Data Channel Standard,” Version 2, Rev. 0, dated Apr. 9, 1996), a Hot Plug Detect (HPD) line (on which the monitor transmits a signal that enables a processor associated with the transmitter to identify the monitor's presence), Analog lines (for transmitting analog video to the receiver), and Power lines (for providing DC power to the receiver and a monitor associated with the receiver). The Display Data Channel standard specifies a protocol for bidirectional communication between a transmitter and a monitor associated with a receiver, including transmission by the monitor of Extended Display Identification (“EDID”) data that specifies various characteristics of the monitor, and transmission by the transmitter of control signals for the monitor. Transmitter 1 includes three identical encoder/serializer units (units 2, 4, and 5) and additional circuitry (not shown). Receiver 3 includes three identical recovery/decoder units (units 8, 10, and 12) and inter-channel alignment circuitry 14 connected as shown, and additional circuitry (not shown).
As shown in FIG. 1, circuit 2 encodes the data to be transmitted over Channel 0, and serializes the encoded bits. Similarly, circuit 4 encodes the data to be transmitted over Channel 1 (and serializes the encoded bits), and circuit 6 encodes the data to be transmitted over Channel 2 (and serializes the encoded bits). Each of circuits 2, 4, and 6 responds to a control signal (an active high binary control signal referred to as a “data enable” or “DE” signal) by selectively encoding either digital video words (in response to DE having a high value) or a control or synchronization signal pair (in response to DE having a low value). Each of encoders 2, 4, and 6 receives a different pair of control or synchronization signals: encoder 2 receives horizontal and vertical synchronization signals (HSYNC and VSYNC); encoder 4 receives control bits CTL0 and CTL1; and encoder 6 receives control bits CTL2 and CTL3. Thus, each of encoders 2, 4, and 6 generates in-band words indicative of video data (in response to DE having a high value), encoder 2 generates out-of-band words indicative of the values of HSYNC and VSYNC (in response to DE having a low value), encoder 4 generates out-of-band words indicative of the values of CTL0 and CTL1 (in response to DE having a low value), and encoder 6 generates out-of-band words indicative of the values of CTL2 and CTL3 (in response to DE having a low value). In response to DE having a low value, each of encoders 4 and 6 generates one of four specific out-of-band words indicative of the values 00, 01, 10, or 11, respectively, of control bits CTL0 and CTL1 (or CTL2 and CTL3).
In operation of the FIG. 1 system, a cable comprising connectors 20 and 21 and conductors 22 is connected between transmitter 1 and receiver 3. Conductors 22 include a conductor pair for transmitting serialized data over Channel 0 from encoder 2 to decoder 8, a conductor pair for transmitting serialized data over Channel 1 from encoder 4 to decoder 10, a conductor pair for transmitting serialized data over Channel 2 from encoder 6 to decoder 12, and a conductor pair for transmitting a video clock over Channel C from transmitter 1 to receiver 3. Conductors 22 also include wires for the DDC channel (which can be used for bidirectional I2C communication between transmitter 1 and receiver 3), a Hot Plug Detect (HPD) line, “Analog” lines for analog video transmission from transmitter 1 to receiver 3, and “Power” lines for provision of power from transmitter 1 to a receiver 3.
In the FIG. 1 system, the frequency of the video clock signal transmitted over Channel C is typically one-tenth the bit rate at which data transmission occurs over each of the data channels (Channels 0, 1, and 2), in the sense that ten data bits are transmitted over each data channel during each video clock period. This can be accomplished by employing nine delay cells in the transmitter to generate nine multiphase delayed versions of the video clock, and using the nine delayed versions of the video clock (each having a different phase) together with the video clock itself to transmit data over each of Channels 0, 1, and 2, at a rate of ten bits per video clock period.
Other serial links include the set of serial links known as Low Voltage Differential Signaling (“LVDS”) links (e.g., “LDI,” the LVDS Display Interface), each of which satisfies the TIA/EIA-644 standard or the IEEE-1596.3 standard, ethernet links, fiberchannel links, serial ATA links used by disk drives, and others.
During high-speed serial data transmission over a link (a cable and/or connectors and/or PCB traces), the link itself introduces losses and dispersion which reduce the signal quality at the receiver end. As the frequency of the transmitted signal and/or the transmission distance increases, the distortion due to frequency dependent delay and attenuation increases, increasing the chance of false detection of signals received and in some cases making the eye at the receiver almost unusable.
Transmission of signals indicative of data (e.g., video or audio data) to a receiver over a serial link degrades the data, for example by introducing time delay error (sometimes referred to as jitter) to the data. In effect, a link applies a filter to the signals during propagation over the link. The filter (to be referred to herein as a “cable filter,” although the link may consist of or include PCB traces) can cause inter-symbol interference (ISI).
Equalization is the application of an inverted version of a cable filter to signals received after propagation over a link. The function of an equalization filter (sometimes referred to as an “equalizer”) is to compensate for, and preferably cancel, the cable filter.
Adaptive equalization has been used to restore signal integrity by compensating for the frequency dependent attenuation that occurs during high speed serial data transmission. However, circuitry for performing the attenuation estimation needed for adaptive equalization has been complex and difficult to implement. This is especially true in the case of circuitry for estimating the attenuation of data transmitted over each of two or more channels of multi-channel serial link, in order to perform adaptive equalization of the data transmitted over each channel.
Various methods have been developed for adaptive equalization. However, equalization circuitry in a receiver cannot easily determine the optimum equalization filter to apply to a received signal unless the receiver knows what the transmitted signal looked like. Without a stable algorithm, adaptive equalization can converge into local minimization or can oscillate, depending on the data pattern itself.